the purpose of designing the JDSP Engine, we intend to use
the CMC (Canadian Microelectronics Corporation) configurable
DSP Platform which includes a basic flow for hardware/software
co-design by providing floating-point design capability for
large dynamic range applications and fixed-point custom design
for computationally-intensive application. It is considered
as an appropriate rapid prototyping step for DSP core-based
ASIC design which is illustrated in the figure below.
approach is adopted to enable reuse Methodology which is the
major reference point for development of an IP block design
flow. The Design Reuse is the key for System on Chip (SoC)
in which the IP is the pre-qualified and standardized for
is a complex integrated circuit (IC) that integrates the
major functional elements of a complete end-product into
a single chip using intellectual property (IP) blocks :
From Board to Chip.
of Design Methodology.
for Design Gap
Present day semiconductor technology allows designers to build
chips with multi millions of transistors.• Future advancements
in technology promise to increase this number even further,
thus allowing complete systems to be built on a single piece
of silicon.• Today SoC includes several modules such
MCU, DSP, VLIW
of Design Methodologies.
Company is aiming a generic design flow for developing soft
IP block, from the starting point of creating a block specification,
to developing and testing behavioral models and the test-bench,
designing sub-blocks, refining the behavioral models to RTL,
and producing and documenting the soft IP block where the sequence
of events is illustrated in the figures below.
IP Block Authoring Flow
Check for Soft IP should be always respected:
how to modify or correct
.Readability: how to read and understand
.Complexity: how to develop and interpret
.Portability: how to use in a different environment
.Reusability: how to use in easy
.Compliance with guidelines: how to follow design rules
.Synthesis efficiency: quality after synthesis
.Testability and verifiability: test pattern, test-bench
.Reliability of the hardware description style: compare behavior
IP blocks are the most flexible and they are represented at
the RTL code (Verilog, VHDL) or netlist level. These IP blocks
are not technology mapped and can be therefore be synthesized
to most fabrication technologies. Soft IP offers further flexibility
in that it can be implemented using a variety of chip technologies,
such as cell-based, gate array, or Field Programmable Gate Array
the end of this stage, the company will be targeting to license
its technology and starting generating revenues.
Firm IP Block
IP blocks are technology mapped in which the designer is allowed
to control the physical layout of the chip. Generally this phase
will be limited to the implementation of the technology on ASIC.
Hard IP Blocks
is the last stage of designing process where the company will
target a specific technology such as wireless modem and which
have a predefined layout that cannot be modified by the System
on Chip (SoC) designers.
process of IP Block Design
Achievable Final Board