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Jaber IP Licensing SOC > - General Design - Soft IP - Firm IP - Hard IP

General design

For the purpose of designing the JDSP Engine, we intend to use the CMC (Canadian Microelectronics Corporation) configurable DSP Platform which includes a basic flow for hardware/software co-design by providing floating-point design capability for large dynamic range applications and fixed-point custom design for computationally-intensive application. It is considered as an appropriate rapid prototyping step for DSP core-based ASIC design which is illustrated in the figure below.

This approach is adopted to enable reuse Methodology which is the major reference point for development of an IP block design flow. The Design Reuse is the key for System on Chip (SoC) in which the IP is the pre-qualified and standardized for design reuse.

What is SoC?

It is a complex integrated circuit (IC) that integrates the major functional elements of a complete end-product into a single chip using intellectual property (IP) blocks :

-Programmable processor.


-Signal Processors.

-On-chip memory.

Soc From Board to Chip.

Transition of Design Methodology.

Core Reuse.

Solution for Design Gap

• Present day semiconductor technology allows designers to build chips with multi millions of transistors.• Future advancements in technology promise to increase this number even further, thus allowing complete systems to be built on a single piece of silicon.• Today SoC includes several modules such as:

– Memories

Evolution of Design Methodologies.



Soft IP

The Company is aiming a generic design flow for developing soft IP block, from the starting point of creating a block specification, to developing and testing behavioral models and the test-bench, designing sub-blocks, refining the behavioral models to RTL, and producing and documenting the soft IP block where the sequence of events is illustrated in the figures below.

Soft IP Block Authoring Flow

Sub-Block Design Flow

Sub-Block Integration Flow

Soft IP Production

Quality Check for Soft IP should be always respected:

.Maintainability: how to modify or correct
.Readability: how to read and understand
.Complexity: how to develop and interpret
.Portability: how to use in a different environment
.Reusability: how to use in easy
.Simulation performance
.Compliance with guidelines: how to follow design rules
.Synthesis efficiency: quality after synthesis
.Testability and verifiability: test pattern, test-bench
.Reliability of the hardware description style: compare behavior

Soft IP blocks are the most flexible and they are represented at the RTL code (Verilog, VHDL) or netlist level. These IP blocks are not technology mapped and can be therefore be synthesized to most fabrication technologies. Soft IP offers further flexibility in that it can be implemented using a variety of chip technologies, such as cell-based, gate array, or Field Programmable Gate Array (FPGA).

At the end of this stage, the company will be targeting to license its technology and starting generating revenues.


Firm IP Block

Firm IP blocks are technology mapped in which the designer is allowed to control the physical layout of the chip. Generally this phase will be limited to the implementation of the technology on ASIC.

Hard IP Blocks

This is the last stage of designing process where the company will target a specific technology such as wireless modem and which have a predefined layout that cannot be modified by the System on Chip (SoC) designers.

Complete process of IP Block Design


JABERTECH Achievable Final Board



The Company That Offers a Unique DSP System Solutions By The Parallel Implementation of Its Innovative DSP Core Engines For The Third Millennium Ultra High Speed Applications